FifoRdFsm.rtl Architecture Reference

Architecture >> FifoRdFsm::rtl

Processes
comb	( doutb , r , rd_en , wrIndex , wrRdy )
seq	( rd_clk , rst )
seq	( rd_clk )
comb	( doutb , r , rd_en , wrIndex , wrRdy )
seq	( rd_clk , rst )
seq	( rd_clk )

Constants
MAX_CNT_C	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 1 ' )
REG_INIT_C	RegType := ( rdRdy = > ite ( FIFO_ASYNC_G , ' 0 ' , ' 1 ' ) , tValid = > ( others = > ' 0 ' ) , enb = > ite ( FWFT_EN_G , ' 0 ' , ' 1 ' ) , regceb = > ite ( FWFT_EN_G , ' 0 ' , ' 1 ' ) , valid = > ' 0 ' , underflow = > ' 0 ' , prog_empty = > ' 1 ' , almost_empty = > ' 1 ' , empty = > ' 1 ' , count = > ( others = > ' 0 ' ) , rdAddr = > ( others = > ' 0 ' ) , rdIndex = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/inferred/FifoRdFsm.vhd
• build/SRC_VHDL/surf/FifoRdFsm.vhd