EventFrameSequencerTb Entity Reference

Inheritance diagram for EventFrameSequencerTb:

Collaboration diagram for EventFrameSequencerTb:

Entities
EventFrameSequencerTb.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TUSER_WIDTH_G	positive range 8 to 8 := 8
TID_WIDTH_G	positive range 8 to 8 := 8
TDEST_WIDTH_G	positive range 8 to 8 := 8
TDATA_NUM_BYTES_G	positive range 8 to 128 := 8

Ports
AXIS_ACLK	in	std_logic := ' 0 '
AXIS_ARESETN	in	std_logic := ' 0 '
S_AXIS0_TVALID	in	std_logic := ' 0 '
S_AXIS0_TDATA	in	std_logic_vector ( ( 8 * TDATA_NUM_BYTES_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS0_TSTRB	in	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS0_TKEEP	in	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS0_TLAST	in	std_logic := ' 0 '
S_AXIS0_TDEST	in	std_logic_vector ( TDEST_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS0_TID	in	std_logic_vector ( TID_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS0_TUSER	in	std_logic_vector ( TUSER_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS0_TREADY	out	std_logic
S_AXIS1_TVALID	in	std_logic := ' 0 '
S_AXIS1_TDATA	in	std_logic_vector ( ( 8 * TDATA_NUM_BYTES_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS1_TSTRB	in	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS1_TKEEP	in	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS1_TLAST	in	std_logic := ' 0 '
S_AXIS1_TDEST	in	std_logic_vector ( TDEST_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS1_TID	in	std_logic_vector ( TID_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS1_TUSER	in	std_logic_vector ( TUSER_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS1_TREADY	out	std_logic
M_AXIS0_TVALID	out	std_logic
M_AXIS0_TDATA	out	std_logic_vector ( ( 8 * TDATA_NUM_BYTES_G ) - 1 downto 0 )
M_AXIS0_TSTRB	out	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 )
M_AXIS0_TKEEP	out	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 )
M_AXIS0_TLAST	out	std_logic
M_AXIS0_TDEST	out	std_logic_vector ( TDEST_WIDTH_G- 1 downto 0 )
M_AXIS0_TID	out	std_logic_vector ( TID_WIDTH_G- 1 downto 0 )
M_AXIS0_TUSER	out	std_logic_vector ( TUSER_WIDTH_G- 1 downto 0 )
M_AXIS0_TREADY	in	std_logic
M_AXIS1_TVALID	out	std_logic
M_AXIS1_TDATA	out	std_logic_vector ( ( 8 * TDATA_NUM_BYTES_G ) - 1 downto 0 )
M_AXIS1_TSTRB	out	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 )
M_AXIS1_TKEEP	out	std_logic_vector ( TDATA_NUM_BYTES_G- 1 downto 0 )
M_AXIS1_TLAST	out	std_logic
M_AXIS1_TDEST	out	std_logic_vector ( TDEST_WIDTH_G- 1 downto 0 )
M_AXIS1_TID	out	std_logic_vector ( TID_WIDTH_G- 1 downto 0 )
M_AXIS1_TUSER	out	std_logic_vector ( TUSER_WIDTH_G- 1 downto 0 )
M_AXIS1_TREADY	in	std_logic
S_AXIL_AWADDR	in	std_logic_vector ( 31 downto 0 )
S_AXIL_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXIL_AWVALID	in	std_logic
S_AXIL_AWREADY	out	std_logic
S_AXIL_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXIL_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXIL_WVALID	in	std_logic
S_AXIL_WREADY	out	std_logic
S_AXIL_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXIL_BVALID	out	std_logic
S_AXIL_BREADY	in	std_logic
S_AXIL_ARADDR	in	std_logic_vector ( 31 downto 0 )
S_AXIL_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXIL_ARVALID	in	std_logic
S_AXIL_ARREADY	out	std_logic
S_AXIL_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXIL_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXIL_RVALID	out	std_logic
S_AXIL_RREADY	in	std_logic

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/EventFrameSequencerTb.vhd
• protocols/event-frame-sequencer/tb/EventFrameSequencerTb.vhd