Architecture >> EventFrameSequencerMux::rtl

Processes
TDEST_REMAP	( sAxisMasters )
comb	( axilReadMaster , axilWriteMaster , axisRst , blowoffExt , r , rxMasters , txSlave )
seq	( axisClk )
TDEST_REMAP	( sAxisMasters )
comb	( axilReadMaster , axilWriteMaster , axisRst , blowoffExt , r , rxMasters , txSlave )
seq	( axisClk )

Constants
LOG2_WIDTH_C	slv ( 3 downto 0 ) := toSlv ( log2 ( AXIS_CONFIG_G.TDATA_BYTES_C ) , 4 )
DEST_SIZE_C	integer := bitSize ( NUM_SLAVES_G- 1 )
REG_INIT_C	RegType := ( softRst = > ' 0 ' , hardRst = > ' 0 ' , blowoffReg = > ' 0 ' , blowoff = > ' 0 ' , cntRst = > ' 0 ' , ready = > ' 0 ' , sof = > ' 1 ' , frameCnt = > ( others = > ' 0 ' ) , numFrames = > ( others = > ' 0 ' ) , seqCnt = > ( others = > ' 0 ' ) , bypass = > ( others = > ' 0 ' ) , dataCnt = > ( others = > ( others = > ' 0 ' ) ) , transCnt = > ( others = > ' 0 ' ) , accept = > ( others = > ' 0 ' ) , transDet = > ( others = > ' 0 ' ) , skipCh = > ( others = > ' 0 ' ) , index = > 0 , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , rxSlaves = > ( others = > AXI_STREAM_SLAVE_INIT_C ) , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
sAxisMastersTmp	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
rxMasters	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
rxSlaves	AxiStreamSlaveArray ( NUM_SLAVES_G- 1 downto 0 )
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_output	AxiStreamPipeline <Entity AxiStreamPipeline>
u_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_output	AxiStreamPipeline <Entity AxiStreamPipeline>

The documentation for this design unit was generated from the following files:

Processes

Constants