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EventFrameSequencerDemux.rtl Architecture Reference
Architecture >> EventFrameSequencerDemux::rtl

Processes

comb  ( axilReadMaster , axilWriteMaster , axisRst , blowoffExt , r , rxMaster , txSlaves )
seq  ( axisClk )
comb  ( axilReadMaster , axilWriteMaster , axisRst , blowoffExt , r , rxMaster , txSlaves )
seq  ( axisClk )

Constants

LOG2_WIDTH_C  slv ( 3 downto 0 ) := toSlv ( log2 ( AXIS_CONFIG_G.TDATA_BYTES_C ) , 4 )
REG_INIT_C  RegType := ( softRst = > ' 0 ' , hardRst = > ' 0 ' , blowoffReg = > ' 0 ' , blowoff = > ' 0 ' , cntRst = > ' 0 ' , sof = > ' 1 ' , frameCnt = > ( others = > ' 0 ' ) , numFrames = > ( others = > ' 0 ' ) , seqCnt = > ( others = > ' 0 ' ) , dataCnt = > ( others = > ( others = > ' 0 ' ) ) , dropCnt = > ( others = > ' 0 ' ) , hdrError = > ( others = > ' 0 ' ) , index = > 0 , tUserFirst = > ( others = > ' 0 ' ) , tDest = > ( others = > ' 0 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMasters = > ( others = > AXI_STREAM_MASTER_INIT_C ) , state = > IDLE_S )

Types

StateType  ( IDLE_S , MOVE_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
rxMaster  AxiStreamMasterType
rxSlave  AxiStreamSlaveType
txMasters  AxiStreamMasterArray ( NUM_MASTERS_G- 1 downto 0 )
txSlaves  AxiStreamSlaveArray ( NUM_MASTERS_G- 1 downto 0 )

Records

RegType 

Instantiations

u_input  AxiStreamPipeline <Entity AxiStreamPipeline>
u_output  AxiStreamPipeline <Entity AxiStreamPipeline>
u_input  AxiStreamPipeline <Entity AxiStreamPipeline>
u_output  AxiStreamPipeline <Entity AxiStreamPipeline>

The documentation for this design unit was generated from the following files: