EthMacRxImportGmii.rtl Architecture Reference

Architecture >> EthMacRxImportGmii::rtl

Processes
comb	( crcIn , crcOut , ethClkEn , ethRst , gmiiRxDv , gmiiRxEr , gmiiRxd , phyReady , r )
seq	( ethClk )

Constants
SFD_C	slv ( 7 downto 0 ) := x " D5 "
AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > INT_EMAC_AXIS_CONFIG_C.TSTRB_EN_C , TDATA_BYTES_C = > 1 , TDEST_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TDEST_BITS_C , TID_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TID_BITS_C , TKEEP_MODE_C = > INT_EMAC_AXIS_CONFIG_C.TKEEP_MODE_C , TUSER_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TUSER_BITS_C , TUSER_MODE_C = > INT_EMAC_AXIS_CONFIG_C.TUSER_MODE_C )
REG_INIT_C	RegType := ( rxCountEn = > ' 0 ' , rxCrcError = > ' 0 ' , crcReset = > ' 0 ' , delRxDv = > ' 0 ' , delRxDvSr = > ( others = > ' 0 ' ) , crcDataValid = > ' 0 ' , sof = > ' 0 ' , state = > WAIT_SFD_S , macData = > ( others = > ' 0 ' ) , macMaster = > AXI_STREAM_MASTER_INIT_C )

Types
StateType	( WAIT_SFD_S , WAIT_DATA_S , GET_DATA_S , DELAY0_S , DELAY1_S , CRC_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
crcOut	slv ( 31 downto 0 )
crcIn	slv ( 31 downto 0 )
macMaster	AxiStreamMasterType

Records
RegType

Instantiations
data_mux	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_crc32	Crc32Parallel <Entity Crc32Parallel>

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd