EthCrc32Parallel.rtl Architecture Reference

Architecture >> EthCrc32Parallel::rtl

Processes
comb	( crcDataValid , crcDataWidth , crcIn , crcReset , dspOut , r )
seq	( crcClk )

Constants
REG_INIT_C	RegType := ( valid = > ' 0 ' , byteWidth = > ( others = > ' 0 ' ) , data = > ( others = > ' 0 ' ) , crc = > CRC_INIT_G )

Signals
r	RegType := REG_INIT_C
rin	RegType
dspInA	Slv96Array ( 31 downto 0 )
dspInB	Slv192Array ( 31 downto 0 )
dspOut	slv ( 31 downto 0 )

Records
RegType

Instantiations
u_xor	DspXor <Entity DspXor>
u_xor	DspXor <Entity DspXor>

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd