Encoder12b14bTb.sim Architecture Reference

Architecture >> Encoder12b14bTb::sim

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false

Signals
clk	sl
clkEn	sl := ' 1 '
rst	sl := not RST_POLARITY_G
dispIn	slv ( 1 downto 0 )
dataIn	slv ( 11 downto 0 )
dataKIn	sl := ' 0 '
dataOut	slv ( 13 downto 0 )
dispOut	slv ( 1 downto 0 )
invalidK	sl
started	boolean := false
run	integer := 0
lastDataOut	slv ( 13 downto 0 )

Shared Variables
runVar	shared integer := := 0

Instantiations
u_clkrst_1	ClkRst <Entity ClkRst>
u_clkrst_1	ClkRst <Entity ClkRst>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Encoder12b14bTb.vhd
• protocols/line-codes/tb/Encoder12b14bTb.vhd