DspAddSubTb.testbed Architecture Reference

Architecture >> DspAddSubTb::testbed

Processes
PROCESS_106	( clk )
PROCESS_215	( clk )

Constants
TPD_G	time := 2 . 5 ns

Signals
clk	sl := ' 0 '
rst	sl := ' 0 '
ain	slv ( 3 downto 0 ) := x " 0 "
bin	slv ( 3 downto 0 ) := x " 0 "
add	slv ( 3 downto 0 ) := x " 0 "
sub	slv ( 3 downto 0 ) := x " 0 "

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_add	DspAddSub <Entity DspAddSub>
u_sub	DspAddSub <Entity DspAddSub>
u_clkrst	ClkRst <Entity ClkRst>
u_add	DspAddSub <Entity DspAddSub>
u_sub	DspAddSub <Entity DspAddSub>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/DspAddSubTb.vhd
• dsp/generic/tb/DspAddSubTb.vhd