Dsp48Comparator4x12b.mapping Architecture Reference

Architecture >> Dsp48Comparator4x12b::mapping

Processes
PROCESS_372	( clk )
PROCESS_373	( clk )

Signals
carryOut	slv ( 3 downto 0 )
din	slv ( 47 downto 0 )
A	slv ( 29 downto 0 )
B	slv ( 17 downto 0 )
C	slv ( 47 downto 0 )
reset	sl
rstDly	sl

Instantiations
dsp48e1_inst	dsp48e1

---

The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/Dsp48Comparator4x12b.vhd