Dsp48Comparator4x12b Entity Reference

Entities
Dsp48Comparator4x12b.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
EN_GREATER_EQUAL_G	boolean := false

Ports
polarity	in	sl := ' 0 '
dataIn	in	Slv12Array ( 0 to 3 )
threshIn	in	Slv12Array ( 0 to 3 )
compOut	out	slv ( 3 downto 0 )
clk	in	sl
rst	in	sl := ' 0 '

---

The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/Dsp48Comparator4x12b.vhd