DeviceDnaUltraScaleTb.testbed Architecture Reference

Architecture >> DeviceDnaUltraScaleTb::testbed

Processes
PROCESS_460	( clk )
PROCESS_461	( failed , passed )

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := CLK_PERIOD_C/ 4
SIM_DNA_VALUE_C	slv ( 95 downto 0 ) := x " 400200000139CA294D9041C5 "

Signals
dnaValue	slv ( 95 downto 0 )
dnaValid	sl
clk	sl := ' 0 '
rst	sl := ' 1 '
passed	sl := ' 0 '
failed	sl := ' 0 '

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_devicednaultrascale	DeviceDnaUltraScale <Entity DeviceDnaUltraScale>

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/tb/DeviceDnaUltraScaleTb.vhd