Delaye3PatchFsm.rtl Architecture Reference

Architecture >> Delaye3PatchFsm::rtl

Processes
comb	( CNTVALUEIN , CNTVALUEOUT , LOAD , r )
seq	( CLK , RST )

Constants
REG_INIT_C	RegType := ( Load = > ' 0 ' , dlyValue = > toSlv ( DELAY_VALUE , 9 ) , dlyTarget = > toSlv ( DELAY_VALUE , 9 ) , waitCnt = > ( others = > ' 0 ' ) , state = > IDLE_S )

Types
StateType	( IDLE_S , CHECK_CNT_S , LOAD_S , WAIT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd