Delaye3PatchFsm Entity Reference

Inheritance diagram for Delaye3PatchFsm:

Entities
Delaye3PatchFsm.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
DELAY_TYPE	string := " FIXED "
DELAY_VALUE	integer := 0
IS_CLK_INVERTED	bit := ' 0 '
IS_RST_INVERTED	bit := ' 0 '

Ports
CLK	in	sl
RST	in	sl
LOAD	in	sl
CNTVALUEIN	in	slv ( 8 downto 0 )
CNTVALUEOUT	in	slv ( 8 downto 0 )
patchLoad	out	sl
patchCntValue	out	slv ( 8 downto 0 )
busy	out	sl

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd