CoaxpressOverFiberGtyUs Entity Reference

Inheritance diagram for CoaxpressOverFiberGtyUs:

Collaboration diagram for CoaxpressOverFiberGtyUs:

Entities
CoaxpressOverFiberGtyUs.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
CoaXPressPkg	Package <CoaXPressPkg>

Generics
TPD_G	time := 1 ns
NUM_LANES_G	positive := 1
STATUS_CNT_WIDTH_G	positive range 1 to 32 := 12
RX_FSM_CNT_WIDTH_G	positive range 1 to 24 := 16
AXIL_BASE_ADDR_G	slv ( 31 downto 0 )
AXIL_CLK_FREQ_G	real
AXIS_CLK_FREQ_G	real
DATA_AXIS_CONFIG_G	AxiStreamConfigType
CFG_AXIS_CONFIG_G	AxiStreamConfigType

Ports
qpllLock	in	Slv2Array ( NUM_LANES_G- 1 downto 0 )
qpllClk	in	Slv2Array ( NUM_LANES_G- 1 downto 0 )
qpllRefclk	in	Slv2Array ( NUM_LANES_G- 1 downto 0 )
qpllRst	out	Slv2Array ( NUM_LANES_G- 1 downto 0 )
gtTxP	out	slv ( NUM_LANES_G- 1 downto 0 )
gtTxN	out	slv ( NUM_LANES_G- 1 downto 0 )
gtRxP	in	slv ( NUM_LANES_G- 1 downto 0 )
gtRxN	in	slv ( NUM_LANES_G- 1 downto 0 )
trigClk	out	sl
trigRst	out	sl
trigger	in	sl
dataClk	in	sl
dataRst	in	sl
dataMaster	out	AxiStreamMasterType
dataSlave	in	AxiStreamSlaveType
imageHdrMaster	out	AxiStreamMasterType
imageHdrSlave	in	AxiStreamSlaveType
cfgClk	in	sl
cfgRst	in	sl
cfgIbMaster	in	AxiStreamMasterType
cfgIbSlave	out	AxiStreamSlaveType
cfgObMaster	out	AxiStreamMasterType
cfgObSlave	in	AxiStreamSlaveType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUs.vhd