CoaXPressRxLane Entity Reference

Inheritance diagram for CoaXPressRxLane:

Entities
CoaXPressRxLane.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
CoaXPressPkg	Package <CoaXPressPkg>
Code8b10bPkg	Package <Code8b10bPkg>

Generics
TPD_G	time := 1 ns

Ports
rxClk	in	sl
rxRst	in	sl
cfgMaster	out	AxiStreamMasterType
dataMaster	out	AxiStreamMasterType
heatbeatMaster	out	AxiStreamMasterType
imageHdrMaster	out	AxiStreamMasterType
ioAck	out	sl
eventAck	out	sl
eventTag	out	slv ( 7 downto 0 )
rxData	in	slv ( 31 downto 0 )
rxDataK	in	slv ( 3 downto 0 )
rxLinkUp	in	sl

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd