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CoaXPressCoreDebugWrapper Entity Reference
+ Inheritance diagram for CoaXPressCoreDebugWrapper:
+ Collaboration diagram for CoaXPressCoreDebugWrapper:

Entities

CoaXPressCoreDebugWrapper.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
SsiPkg  Package <SsiPkg>

Generics

FORCE_RX_CTRL_G  boolean := false

Ports

dataClk   in   sl
dataRst   in   sl
cfgClk   in   sl
cfgRst   in   sl
txClk   in   sl
txRst   in   sl
rxClk   in   sl
rxRst   in   sl
axilClk   in   sl
axilRst   in   sl
txTrig   in   sl
txLinkUp   in   sl
rxData   in   slv ( 31 downto 0 )
rxDataK   in   slv ( 3 downto 0 )
rxDispErr   in   sl
rxDecErr   in   sl
rxLinkUp   in   sl
gtRstAll   out   sl
txLsValid   out   sl
txLsData   out   slv ( 7 downto 0 )
txLsDataK   out   sl
txLsRate   out   sl
txLsLaneEn   out   slv ( 3 downto 0 )
DBG_RX_FSM_RST   out   sl
DBG_RX_NUM_OF_LANE   out   slv ( 2 downto 0 )
DBG_RX_OVERFLOW   out   sl
DBG_RX_FSM_ERROR   out   sl
DBG_AXIL_OVERFLOW   out   sl
DBG_AXIL_FSM_ERROR   out   sl
S_AXI_AWADDR   in   slv ( 11 downto 0 )
S_AXI_AWPROT   in   slv ( 2 downto 0 )
S_AXI_AWVALID   in   sl
S_AXI_AWREADY   out   sl
S_AXI_WDATA   in   slv ( 31 downto 0 )
S_AXI_WSTRB   in   slv ( 3 downto 0 )
S_AXI_WVALID   in   sl
S_AXI_WREADY   out   sl
S_AXI_BRESP   out   slv ( 1 downto 0 )
S_AXI_BVALID   out   sl
S_AXI_BREADY   in   sl
S_AXI_ARADDR   in   slv ( 11 downto 0 )
S_AXI_ARPROT   in   slv ( 2 downto 0 )
S_AXI_ARVALID   in   sl
S_AXI_ARREADY   out   sl
S_AXI_RDATA   out   slv ( 31 downto 0 )
S_AXI_RRESP   out   slv ( 1 downto 0 )
S_AXI_RVALID   out   sl
S_AXI_RREADY   in   sl
S_CFG_IB_TVALID   in   sl
S_CFG_IB_TDATA   in   slv ( 255 downto 0 )
S_CFG_IB_TKEEP   in   slv ( 31 downto 0 )
S_CFG_IB_TLAST   in   sl
S_CFG_IB_TUSER   in   slv ( 1 downto 0 )
S_CFG_IB_TREADY   out   sl
M_CFG_OB_TVALID   out   sl
M_CFG_OB_TDATA   out   slv ( 255 downto 0 )
M_CFG_OB_TKEEP   out   slv ( 31 downto 0 )
M_CFG_OB_TLAST   out   sl
M_CFG_OB_TUSER   out   slv ( 1 downto 0 )
M_CFG_OB_TREADY   in   sl
M_DATA_TVALID   out   sl
M_DATA_TDATA   out   slv ( 31 downto 0 )
M_DATA_TKEEP   out   slv ( 3 downto 0 )
M_DATA_TLAST   out   sl
M_DATA_TUSER   out   slv ( 0 downto 0 )
M_DATA_TREADY   in   sl
M_HDR_TVALID   out   sl
M_HDR_TDATA   out   slv ( 31 downto 0 )
M_HDR_TKEEP   out   slv ( 3 downto 0 )
M_HDR_TLAST   out   sl
M_HDR_TUSER   out   slv ( 0 downto 0 )
M_HDR_TREADY   in   sl

The documentation for this design unit was generated from the following file: