ClockDivider.rtl Architecture Reference

Architecture >> ClockDivider::rtl

Processes
comb	( delayCount , highCount , lowCount , r , rst )
seq	( clk , rst )
comb	( delayCount , highCount , lowCount , r , rst )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( state = > DELAY_S , divClk = >not LEADING_EDGE_G , preRise = > ' 0 ' , preFall = > ' 0 ' , counter = > ( others = > ' 0 ' ) )

Types
StateType	( DELAY_S , CLOCK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/general/rtl/ClockDivider.vhd
• build/SRC_VHDL/surf/ClockDivider.vhd