ClockDivider Entity Reference

Entities
ClockDivider.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
LEADING_EDGE_G	sl := ' 1 '
COUNT_WIDTH_G	integer range 1 to 32 := 16

Ports
clk	in	sl
rst	in	sl
highCount	in	slv ( COUNT_WIDTH_G- 1 downto 0 )
lowCount	in	slv ( COUNT_WIDTH_G- 1 downto 0 )
delayCount	in	slv ( COUNT_WIDTH_G- 1 downto 0 )
divClk	out	sl
preRise	out	sl
preFall	out	sl

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The documentation for this design unit was generated from the following files:

• base/general/rtl/ClockDivider.vhd
• build/SRC_VHDL/surf/ClockDivider.vhd