BoxcarFilter.mapping Architecture Reference

Architecture >> BoxcarFilter::mapping

Signals
intData	slv ( DATA_WIDTH_G+ ADDR_WIDTH_G- 1 downto 0 )

Instantiations
u_integrator	BoxcarIntegrator <Entity BoxcarIntegrator>
u_integrator	BoxcarIntegrator <Entity BoxcarIntegrator>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/BoxcarFilter.vhd
• dsp/generic/fixed/BoxcarFilter.vhd