BRAM2.rtl Architecture Reference

Architecture >> BRAM2::rtl

Processes
PROCESS_112	( CLKA )
PROCESS_113	( CLKB )

Types
MemType	( 0 to MEMSIZE_G- 1 ) slv ( DATA_WIDTH_G- 1 downto 0 )

Signals
doaR	slv ( DATA_WIDTH_G- 1 downto 0 )
dobR	slv ( DATA_WIDTH_G- 1 downto 0 )
doaR2	slv ( DATA_WIDTH_G- 1 downto 0 )
dobR2	slv ( DATA_WIDTH_G- 1 downto 0 )

Shared Variables
mem	shared MemType

---

The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/blue-lib/BRAM2.vhd