BRAM2 Entity Reference

Inheritance diagram for BRAM2:

Entities
BRAM2.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
PIPELINED_G	natural := 0
ADDR_WIDTH_G	positive := 1
DATA_WIDTH_G	positive := 1
MEMSIZE_G	positive := 1

Ports
CLKA	in	sl
ENA	in	sl
WEA	in	sl
ADDRA	in	slv ( ADDR_WIDTH_G- 1 downto 0 )
DIA	in	slv ( DATA_WIDTH_G- 1 downto 0 )
DOA	out	slv ( DATA_WIDTH_G- 1 downto 0 )
CLKB	in	sl
ENB	in	sl
WEB	in	sl
ADDRB	in	slv ( ADDR_WIDTH_G- 1 downto 0 )
DIB	in	slv ( DATA_WIDTH_G- 1 downto 0 )
DOB	out	slv ( DATA_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/blue-lib/BRAM2.vhd