AxisToJtagTb.AxisToJtagTbImpl Architecture Reference

Architecture >> AxisToJtagTb::AxisToJtagTbImpl

Processes
P_TX	( clk )
P_RX	( clk )
P_CLK

Procedures
	send( xin: in Word , del: in natural 0 )
	sendVec( xin: in WordArray )
	rcv( expin: in Word , lst: in sl )
	rcvVec( exp: in WordArray )

Constants
TPD_C	time := 5 ns

Types
WordArray	array ( natural range <> ) of Word

Subtypes
Word	slv ( 31 downto 0 )

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
mAxisTdi	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisTdi	AxiStreamSlaveType
mAxisTdo	AxiStreamMasterType
sAxisTdo	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
loopback	sl
run	boolean := true
txstage	natural := 0
rxstage	natural := 0
td	Word
tv	sl := ' 0 '
tl	sl
tr	sl
rd	Word
rv	sl := ' 0 '
rl	sl
rr	sl

Instantiations
u_dut	AxisToJtag <Entity AxisToJtag>

---

The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/tb/AxisToJtagTb.vhd