AxisToJtagCoreTb.AxisToJtagCoreTbImpl Architecture Reference

Architecture >> AxisToJtagCoreTb::AxisToJtagCoreTbImpl

Processes
PROCESS_451
P_TX	( clk )
P_RX	( clk )
P_RST	( clk )

Constants
W_C	positive := 2
WB_C	positive := 8 * W_C

Types
WordArray	array ( natural range <> ) of slv ( WB_C- 1 downto 0 )

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
rsttx	sl := ' 1 '
run	boolean := true
tdi	sl
tdo	sl
tck	sl
mAxisTdi	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisTdi	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mAxisTdo	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisTdo	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
stage	natural := 0
res	WordArray ( 0 to 4 )
ridx	natural := 0
tidx	natural := 0
tvGate	boolean := true
rrGate	boolean := true
rxDon	boolean := false
del	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
txData	WordArray ( 0 to 6 ) := ( x " 0021 " , x " 0000 " , x " DEAD " , x " 0000 " , x " 3210 " , x " 0000 " , x " 0002 " )

Instantiations
u_dut	AxisToJtagCore <Entity AxisToJtagCore>

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/tb/AxisToJtagCoreTb.vhd