AxiWritePathMux.structure Architecture Reference

Architecture >> AxiWritePathMux::structure

Processes
comb	( axiRst , mAxiWriteSlave , r , sAxiWriteMasters )
seq	( axiClk )
comb	( axiRst , mAxiWriteSlave , r , sAxiWriteMasters )
seq	( axiClk )

Constants
DEST_SIZE_C	integer := bitSize ( NUM_SLAVES_G- 1 )
ARB_BITS_C	integer := 2 ** DEST_SIZE_C
REG_INIT_C	RegType := ( addrState = > S_IDLE_C , addrAcks = > ( others = > ' 0 ' ) , addrAckNum = > ( others = > ' 0 ' ) , addrValid = > ' 0 ' , dataReq = > ' 0 ' , dataAck = > ' 0 ' , dataState = > S_IDLE_C , dataAckNum = > ( others = > ' 0 ' ) , slaves = > ( others = > AXI_WRITE_SLAVE_INIT_C ) , master = > AXI_WRITE_MASTER_INIT_C )

Types
StateType	( S_IDLE_C , S_MOVE_C , S_LAST_C , S_WAIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiWritePathMux.vhd
• build/SRC_VHDL/surf/AxiWritePathMux.vhd