AxiWritePathMux Entity Reference

Entities
AxiWritePathMux.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
ArbiterPkg	Package <ArbiterPkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
NUM_SLAVES_G	integer range 1 to 32 := 4

Ports
axiClk	in	sl
axiRst	in	sl
sAxiWriteMasters	in	AxiWriteMasterArray ( NUM_SLAVES_G- 1 downto 0 )
sAxiWriteSlaves	out	AxiWriteSlaveArray ( NUM_SLAVES_G- 1 downto 0 )
mAxiWriteMaster	out	AxiWriteMasterType
mAxiWriteSlave	in	AxiWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiWritePathMux.vhd
• build/SRC_VHDL/surf/AxiWritePathMux.vhd