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AxiSy56040Core Entity Reference
Inheritance diagram for AxiSy56040Core: Collaboration diagram for AxiSy56040Core:Entities | |
| AxiSy56040Core.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| AxiSy56040Pkg | Package <AxiSy56040Pkg> |
Generics | |
| TPD_G | time := 1 ns |
| AXI_CLK_FREQ_G | real := 200 . 0E + 6 |
| XBAR_DEFAULT_G | Slv2Array ( 3 downto 0 ) := ( " 11 " , " 10 " , " 01 " , " 00 " ) |
Ports | ||
| xBar | out | AxiSy56040OutType |
| axiReadMaster | in | AxiLiteReadMasterType |
| axiReadSlave | out | AxiLiteReadSlaveType |
| axiWriteMaster | in | AxiLiteWriteMasterType |
| axiWriteSlave | out | AxiLiteWriteSlaveType |
| axiClk | in | sl |
| axiRst | in | sl |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/AxiSy56040Core.vhd
- devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd
