AxiStreamTrailerRemove.rtl Architecture Reference

Architecture >> AxiStreamTrailerRemove::rtl

Processes
comb	( axisMasterPipe , axisRst , axisSlaveToPipe , pipeAxisSlave , r , sAxisMaster )
seq	( axisClk , axisRst )
comb	( axisMasterPipe , axisRst , axisSlaveToPipe , pipeAxisSlave , r , sAxisMaster )
seq	( axisClk , axisRst )

Constants
BYTES_C	positive := AXI_CONFIG_G.TDATA_BYTES_C
REG_INIT_C	RegType := ( obMaster = > axiStreamMasterInit ( AXI_CONFIG_G ) , ibSlave = > AXI_STREAM_SLAVE_INIT_C , regularTLast = > true )

Signals
r	RegType := REG_INIT_C
rin	RegType
pipeAxisMaster	AxiStreamMasterType
pipeAxisSlave	AxiStreamSlaveType
axisMasterToPipe	AxiStreamMasterType
axisSlaveToPipe	AxiStreamSlaveType
axisMasterPipe	AxiStreamMasterType
axisSlavePipe	AxiStreamSlaveType

Records
RegType

Instantiations
axistreampipeline_2	AxiStreamPipeline <Entity AxiStreamPipeline>
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>
axistreampipeline_2	AxiStreamPipeline <Entity AxiStreamPipeline>
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamTrailerRemove.vhd
• build/SRC_VHDL/surf/AxiStreamTrailerRemove.vhd