AxiStreamShift.rtl Architecture Reference

Architecture >> AxiStreamShift::rtl

Processes
comb	( axiShiftCnt , axiShiftDir , axiStart , axisRst , pipeAxisSlave , r , sAxisMaster )
seq	( axisClk , axisRst )
comb	( axiShiftCnt , axiShiftDir , axiStart , axisRst , pipeAxisSlave , r , sAxisMaster )
seq	( axisClk , axisRst )

Procedures
	shiftData( shiftBytes: in slv ( 3 downto 0 ) shiftDir: in sl shiftFirst: in boolean mInput: in AxiStreamMasterType mDelay: in AxiStreamMasterType mOut: inout AxiStreamMasterType )
	shiftData( shiftBytes: in slv ( 3 downto 0 ) shiftDir: in sl shiftFirst: in boolean mInput: in AxiStreamMasterType mDelay: in AxiStreamMasterType mOut: inout AxiStreamMasterType )

Constants
REG_INIT_C	RegType := ( state = > S_IDLE_C , shiftDir = > ' 0 ' , shiftBytes = > ( others = > ' 0 ' ) , slave = > AXI_STREAM_SLAVE_INIT_C , master = > AXI_STREAM_MASTER_INIT_C , delay = > AXI_STREAM_MASTER_INIT_C )

Types
StateType	( S_IDLE_C , S_FIRST_C , S_SHIFT_C , S_LAST_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
pipeAxisMaster	AxiStreamMasterType
pipeAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamShift.vhd
• build/SRC_VHDL/surf/AxiStreamShift.vhd