AxiStreamPkgTb.testbed Architecture Reference

Architecture >> AxiStreamPkgTb::testbed

Processes
comb	( r , rst )
seq	( clk )
PROCESS_12	( failed , passed )
comb	( r , rst )
seq	( clk )
PROCESS_92	( failed , passed )

Constants
CLK_PERIOD_C	time := 4 ns
TPD_C	time := CLK_PERIOD_C/ 4
REG_INIT_C	RegType := ( passed = > ' 0 ' , passedDly = > ' 0 ' , failed = > ' 0 ' , failedDly = > ' 0 ' , tKeepResult = > ( others = > ' 0 ' ) , tKeepExpected = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl := ' 0 '
rst	sl := ' 0 '
passed	sl := ' 0 '
failed	sl := ' 0 '

Records
RegType

Instantiations
clkrst_inst	ClkRst <Entity ClkRst>
clkrst_inst	ClkRst <Entity ClkRst>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/tb/AxiStreamPkgTb.vhd
• build/SRC_VHDL/surf/AxiStreamPkgTb.vhd