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AxiStreamGearbox.rtl Architecture Reference
Architecture >> AxiStreamGearbox::rtl

Processes

comb  ( axisRst , pipeAxisSlave , r , sAxisMaster , sSideBand )
seq  ( axisClk , axisRst )
comb  ( axisRst , pipeAxisSlave , r , sAxisMaster , sSideBand )
seq  ( axisClk , axisRst )

Constants

SLV_BYTES_C  positive := SLAVE_AXI_CONFIG_G.TDATA_BYTES_C
MST_BYTES_C  positive := MASTER_AXI_CONFIG_G.TDATA_BYTES_C
SLV_USER_C  positive := ite ( SLAVE_AXI_CONFIG_G.TUSER_BITS_C/ = 0 , SLAVE_AXI_CONFIG_G.TUSER_BITS_C , 1 )
MST_USER_C  positive := ite ( MASTER_AXI_CONFIG_G.TUSER_BITS_C/ = 0 , MASTER_AXI_CONFIG_G.TUSER_BITS_C , 1 )
WORD_MULTIPLE_C  boolean := ( SLV_BYTES_C> = MST_BYTES_Cand SLV_BYTES_Cmod MST_BYTES_C = 0 ) or ( MST_BYTES_C> = SLV_BYTES_Cand MST_BYTES_Cmod SLV_BYTES_C = 0 )
TSTRB_EN_C  boolean := SLAVE_AXI_CONFIG_G.TSTRB_EN_Cand MASTER_AXI_CONFIG_G.TSTRB_EN_C
TDEST_EN_C  boolean := ( SLAVE_AXI_CONFIG_G.TDEST_BITS_C> 0 ) and ( MASTER_AXI_CONFIG_G.TDEST_BITS_C> 0 )
TID_EN_C  boolean := ( SLAVE_AXI_CONFIG_G.TID_BITS_C> 0 ) and ( MASTER_AXI_CONFIG_G.TID_BITS_C> 0 )
TUSER_EN_C  boolean := ( SLAVE_AXI_CONFIG_G.TUSER_BITS_C> 0 ) and ( MASTER_AXI_CONFIG_G.TUSER_BITS_C> 0 ) and ( SLAVE_AXI_CONFIG_G.TUSER_MODE_C/ = TUSER_NONE_C ) and ( MASTER_AXI_CONFIG_G.TUSER_MODE_C/ = TUSER_NONE_C )
TDEST_BITS_C  natural := ite ( TDEST_EN_C , minimum ( SLAVE_AXI_CONFIG_G.TDEST_BITS_C , MASTER_AXI_CONFIG_G.TDEST_BITS_C ) , 1 )
TID_BITS_C  natural := ite ( TID_EN_C , minimum ( SLAVE_AXI_CONFIG_G.TID_BITS_C , MASTER_AXI_CONFIG_G.TID_BITS_C ) , 1 )
TUSER_BITS_C  natural := ite ( TUSER_EN_C , minimum ( SLAVE_AXI_CONFIG_G.TUSER_BITS_C , MASTER_AXI_CONFIG_G.TUSER_BITS_C ) , 1 )
MAX_C  positive := maximum ( MST_BYTES_C , SLV_BYTES_C )
MIN_C  positive := minimum ( MST_BYTES_C , SLV_BYTES_C )
SHIFT_WIDTH_C  positive := wordCount ( MAX_C , MIN_C ) * MIN_C+ MIN_C
REG_INIT_C  RegType := ( writeIndex = > 0 , tValid = > ' 0 ' , tData = > ( others = > ' 0 ' ) , tStrb = > ( others = > ' 0 ' ) , tKeep = > ( others = > ' 0 ' ) , tLast = > ' 0 ' , tLastDly = > ' 0 ' , tDest = > ( others = > ' 0 ' ) , tId = > ( others = > ' 0 ' ) , tUser = > ( others = > ' 0 ' ) , sideBand = > ( others = > ' 0 ' ) , sAxisSlave = > AXI_STREAM_SLAVE_INIT_C )

Signals

r  RegType := REG_INIT_C
rin  RegType
pipeAxisMaster  AxiStreamMasterType
pipeSideBand  slv ( SIDE_BAND_WIDTH_G- 1 downto 0 )
pipeAxisSlave  AxiStreamSlaveType

Records

RegType 

Instantiations

u_resize  AxiStreamResize <Entity AxiStreamResize>
u_pipeline  AxiStreamPipeline <Entity AxiStreamPipeline>
u_resize  AxiStreamResize <Entity AxiStreamResize>
u_pipeline  AxiStreamPipeline <Entity AxiStreamPipeline>

The documentation for this design unit was generated from the following files: