AxiStreamGearboxUnpack.rtl Architecture Reference

Architecture >> AxiStreamGearboxUnpack::rtl

Processes
comb	( axisRst , packedSsiMaster , r )
seq	( axisClk , axisRst )
comb	( axisRst , packedSsiMaster , r )
seq	( axisClk , axisRst )

Constants
STREAM_WIDTH_C	integer := AXI_STREAM_CONFIG_G.TDATA_BYTES_C* 8
PACK_SIZE_C	integer := RANGE_HIGH_G- RANGE_LOW_G+ 1
SIZE_DIFFERENCE_C	integer := STREAM_WIDTH_C- PACK_SIZE_C
ZERO_C	slv ( SIZE_DIFFERENCE_C- 1 downto 0 ) := slvZero ( SIZE_DIFFERENCE_C )
REG_INIT_C	RegType := ( packedSsiSlave = > ssiSlaveInit ( AXI_STREAM_CONFIG_G ) , rawSsiMaster = > ssiMasterInit ( AXI_STREAM_CONFIG_G ) , data = > ( others = > ' 0 ' ) , splitIndex = > ( others = > ' 0 ' ) , eof = > ' 0 ' , eofe = > ' 0 ' , doLast = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
rawSsiSlave	SsiSlaveType
packedSsiMaster	SsiMasterType
locRawAxisMaster	AxiStreamMasterType
locRawAxisSlave	AxiStreamSlaveType
locRawAxisCtrl	AxiStreamCtrlType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd
• build/SRC_VHDL/surf/AxiStreamGearboxUnpack.vhd