SURF
Loading...
Searching...
No Matches
AxiStreamFrameBufferTb.testbed Architecture Reference
Architecture >> AxiStreamFrameBufferTb::testbed

Processes

comb  ( r , dataRst )
seq  ( dataClk )

Constants

CLK_PERIOD_C  time := 10 ns
TPD_C  time := CLK_PERIOD_C/ 4
AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 2 )
REG_INIT_C  RegType := ( data = > ( others = > ' 0 ' ) , dataValid = > ' 0 ' , frameDone = > ' 0 ' , cnt = > ( others = > ' 0 ' ) , dataRdTrig = > ' 0 ' , axilRdTrig = > ' 0 ' )

Signals

r  RegType := REG_INIT_C
rin  RegType
dataClk  sl := ' 0 '
dataRst  sl := ' 1 '
axiClk  sl := ' 0 '
axiRst  sl := ' 1 '
axilWriteMaster  AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave  AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axilReadMaster  AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave  AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axisMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Records

RegType 

Instantiations

u_dataclkrst  ClkRst <Entity ClkRst>
u_axiclkrst  ClkRst <Entity ClkRst>
u_dut  AxiStreamFrameBuffer <Entity AxiStreamFrameBuffer>

The documentation for this design unit was generated from the following file: