AxiStreamDmaWriteIpIntegrator Entity Reference

Inheritance diagram for AxiStreamDmaWriteIpIntegrator:

Collaboration diagram for AxiStreamDmaWriteIpIntegrator:

Entities
AxiStreamDmaWriteIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Ports
axiClk	in	sl
axiRst	in	sl
dmaReqRequest	in	sl
dmaReqDrop	in	sl
dmaReqAddress	in	slv ( 63 downto 0 )
dmaReqMaxSize	in	slv ( 31 downto 0 )
dmaReqProt	in	slv ( 2 downto 0 )
dmaAckDone	out	sl
dmaAckIdle	out	sl
dmaAckSize	out	slv ( 31 downto 0 )
dmaAckOverflow	out	sl
dmaAckWriteError	out	sl
dmaAckErrorValue	out	slv ( 1 downto 0 )
dmaAckFirstUser	out	slv ( 7 downto 0 )
dmaAckLastUser	out	slv ( 7 downto 0 )
dmaAckDest	out	slv ( 7 downto 0 )
dmaAckId	out	slv ( 7 downto 0 )
axiCache	in	slv ( 3 downto 0 )
S_AXIS_TVALID	in	sl
S_AXIS_TDATA	in	slv ( 63 downto 0 )
S_AXIS_TKEEP	in	slv ( 7 downto 0 )
S_AXIS_TLAST	in	sl
S_AXIS_TDEST	in	slv ( 7 downto 0 )
S_AXIS_TID	in	slv ( 7 downto 0 )
S_AXIS_TUSER	in	slv ( 1 downto 0 )
S_AXIS_TREADY	out	sl
M_AXI_AWID	out	slv ( 7 downto 0 )
M_AXI_AWADDR	out	slv ( 15 downto 0 )
M_AXI_AWLEN	out	slv ( 7 downto 0 )
M_AXI_AWSIZE	out	slv ( 2 downto 0 )
M_AXI_AWBURST	out	slv ( 1 downto 0 )
M_AXI_AWLOCK	out	sl
M_AXI_AWCACHE	out	slv ( 3 downto 0 )
M_AXI_AWPROT	out	slv ( 2 downto 0 )
M_AXI_AWREGION	out	slv ( 3 downto 0 )
M_AXI_AWQOS	out	slv ( 3 downto 0 )
M_AXI_AWVALID	out	sl
M_AXI_AWREADY	in	sl
M_AXI_WID	out	slv ( 7 downto 0 )
M_AXI_WDATA	out	slv ( 63 downto 0 )
M_AXI_WSTRB	out	slv ( 7 downto 0 )
M_AXI_WLAST	out	sl
M_AXI_WVALID	out	sl
M_AXI_WREADY	in	sl
M_AXI_BID	in	slv ( 7 downto 0 )
M_AXI_BRESP	in	slv ( 1 downto 0 )
M_AXI_BVALID	in	sl
M_AXI_BREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd