AxiStreamBytePacker.rtl Architecture Reference

Architecture >> AxiStreamBytePacker::rtl

Processes
comb	( axiRst , r , sAxisMaster )
seq	( axiClk , axiRst )
comb	( axiRst , r , sAxisMaster )
seq	( axiClk , axiRst )

Constants
SLV_TUSER_BITS_C	natural := ite ( SLAVE_CONFIG_G.TUSER_BITS_C/ = 0 , SLAVE_CONFIG_G.TUSER_BITS_C , 1 )
MAX_IN_BYTE_C	integer := SLAVE_CONFIG_G.TDATA_BYTES_C- 1
MAX_OUT_BYTE_C	integer := MASTER_CONFIG_G.TDATA_BYTES_C- 1
REG_INIT_C	RegType := ( byteCount = > 0 , inTop = > 0 , inMaster = > AXI_STREAM_MASTER_INIT_C , curMaster = > AXI_STREAM_MASTER_INIT_C , nxtMaster = > AXI_STREAM_MASTER_INIT_C , outMaster = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamBytePacker.vhd
• protocols/packetizer/rtl/AxiStreamBytePacker.vhd