AxiResize.rtl Architecture Reference

Architecture >> AxiResize::rtl

Processes
comb	( axiRst , mAxiReadSlave , mAxiWriteSlave , r , sAxiReadMaster , sAxiWriteMaster )
seq	( axiClk )
comb	( axiRst , mAxiReadSlave , mAxiWriteSlave , r , sAxiReadMaster , sAxiWriteMaster )
seq	( axiClk )

Constants
SLV_BYTES_C	integer := SLAVE_AXI_CONFIG_G.DATA_BYTES_C
MST_BYTES_C	integer := MASTER_AXI_CONFIG_G.DATA_BYTES_C
MAX_BYTES_C	integer := maximum ( SLV_BYTES_C , MST_BYTES_C )
COUNT_C	integer := ite ( SLV_BYTES_C> MST_BYTES_C , SLV_BYTES_C/ MST_BYTES_C , MST_BYTES_C/ SLV_BYTES_C )
BIT_CNT_C	integer := bitSize ( COUNT_C )
SHIFT_C	integer := log2 ( COUNT_C )
REG_INIT_C	RegType := ( rdCount = > ( others = > ' 0 ' ) , rdMaster = > axiReadMasterInit ( MASTER_AXI_CONFIG_G ) , rdSlave = > AXI_READ_SLAVE_INIT_C , wrCount = > ( others = > ' 0 ' ) , wrMaster = > axiWriteMasterInit ( MASTER_AXI_CONFIG_G ) , wrSlave = > AXI_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiResize.vhd
• build/SRC_VHDL/surf/AxiResize.vhd