AxiResize Entity Reference

Entities
AxiResize.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
SLAVE_AXI_CONFIG_G	AxiConfigType
MASTER_AXI_CONFIG_G	AxiConfigType

Ports
axiClk	in	sl
axiRst	in	sl
sAxiReadMaster	in	AxiReadMasterType
sAxiReadSlave	out	AxiReadSlaveType
sAxiWriteMaster	in	AxiWriteMasterType
sAxiWriteSlave	out	AxiWriteSlaveType
mAxiReadMaster	out	AxiReadMasterType
mAxiReadSlave	in	AxiReadSlaveType
mAxiWriteMaster	out	AxiWriteMasterType
mAxiWriteSlave	in	AxiWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiResize.vhd
• build/SRC_VHDL/surf/AxiResize.vhd