AxiMicronP30Reg Entity Reference

Inheritance diagram for AxiMicronP30Reg:

Collaboration diagram for AxiMicronP30Reg:

Entities
AxiMicronP30Reg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
EN_PASSWORD_LOCK_G	boolean := false
PASSWORD_LOCK_G	slv ( 31 downto 0 ) := x " DEADBEEF "
MEM_ADDR_MASK_G	slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G	real := 200 . 0E + 6

Ports
flashAddr	out	slv ( 30 downto 0 )
flashAdv	out	sl
flashClk	out	sl
flashRstL	out	sl
flashCeL	out	sl
flashOeL	out	sl
flashWeL	out	sl
flashTri	out	sl
flashDin	out	slv ( 15 downto 0 )
flashDout	in	slv ( 15 downto 0 )
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
axiClk	in	sl
axiRst	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Micron/p30/rtl/AxiMicronP30Reg.vhd