AxiMicronP30Core Entity Reference

Inheritance diagram for AxiMicronP30Core:

Collaboration diagram for AxiMicronP30Core:

Entities
AxiMicronP30Core.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiMicronP30Pkg	Package <AxiMicronP30Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
EN_PASSWORD_LOCK_G	boolean := false
PASSWORD_LOCK_G	slv ( 31 downto 0 ) := x " DEADBEEF "
MEM_ADDR_MASK_G	slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G	real := 200 . 0E + 6

Ports
flashIn	in	AxiMicronP30InType
flashInOut	inout	AxiMicronP30InOutType
flashOut	out	AxiMicronP30OutType
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
axiClk	in	sl
axiRst	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Micron/p30/rtl/AxiMicronP30Core.vhd