Architecture >> AxiMicronN25QReg::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , busyIn , miso , r , ramDout )
seq	( axiClk )

Constants
DOUBLE_SCK_FREQ_C	*real := SPI_CLK_FREQ_G 2 . 0**
SCK_HALF_PERIOD_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , DOUBLE_SCK_FREQ_C ) ) - 1
MIN_CS_WIDTH_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , 2 . 0E + 7 ) )
MAX_SCK_CNT_C	natural := ite ( ( SCK_HALF_PERIOD_C> MIN_CS_WIDTH_C ) , SCK_HALF_PERIOD_C , MIN_CS_WIDTH_C )
PRESET_32BIT_ADDR_C	slv ( 8 downto 0 ) := " 111111011 "
PRESET_24BIT_ADDR_C	slv ( 8 downto 0 ) := " 111111100 "
REG_INIT_C	RegType := ( test = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) , rdData = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , addr32BitMode = > ' 0 ' , cmd = > ( others = > ' 0 ' ) , status = > ( others = > ' 0 ' ) , RnW = > ' 1 ' , we = > ' 0 ' , rd = > " 00 " , cnt = > ( others = > ' 0 ' ) , waddr = > ( others = > ' 0 ' ) , raddr = > ( others = > ' 0 ' ) , xferSize = > ( others = > ' 0 ' ) , ramDin = > ( others = > ' 0 ' ) , busy = > ' 0 ' , csL = > ' 1 ' , sck = > ' 0 ' , mosi = > ' 0 ' , sckCnt = > 0 , bitPntr = > 0 , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , WORD_WRITE_S , WORD_READ_S , SCK_LOW_S , SCK_HIGH_S , MIN_CS_WIDTH_S )

Records
RegType

Instantiations
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>

The documentation for this design unit was generated from the following file:

Processes

Constants