AxiMicronN25QCore Entity Reference

Inheritance diagram for AxiMicronN25QCore:

Collaboration diagram for AxiMicronN25QCore:

Entities
AxiMicronN25QCore.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
EN_PASSWORD_LOCK_G	boolean := false
PASSWORD_LOCK_G	slv ( 31 downto 0 ) := x " DEADBEEF "
MEM_ADDR_MASK_G	slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G	real := 200 . 0E + 6
SPI_CLK_FREQ_G	real := 25 . 0E + 6

Ports
csL	out	sl
sck	out	sl
mosi	out	sl
miso	in	sl
busyIn	in	sl := ' 0 '
busyOut	out	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
axiClk	in	sl
axiRst	in	sl

---

The documentation for this design unit was generated from the following file:

• devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd