Architecture >> AxiMicronMt28ewReg::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , flashDo , r , ramDout )
seq	( axiClk )

Constants
HALF_CYCLE_PERIOD_C	real := 64 . 0E - 9
HALF_CYCLE_FREQ_C	real := ( 1 . 0 / HALF_CYCLE_PERIOD_C )
MAX_CNT_C	natural := getTimeRatio ( AXI_CLK_FREQ_G , HALF_CYCLE_FREQ_C )
REG_INIT_C	RegType := ( tristate = > ' 1 ' , ceL = > ' 1 ' , oeL = > ' 1 ' , RnW = > ' 1 ' , weL = > ' 1 ' , cnt = > 0 , din = > x " 0000 " , dataReg = > x " 0000 " , baseAddr = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) , test = > ( others = > ' 0 ' ) , blockRd = > ' 0 ' , blockWr = > ' 0 ' , blockCnt = > ( others = > ' 0 ' ) , xferSize = > ( others = > ' 0 ' ) , ramRd = > ( others = > ' 0 ' ) , ramWe = > ' 0 ' , ramDin = > ( others = > ' 0 ' ) , waddr = > ( others = > ' 0 ' ) , raddr = > ( others = > ' 0 ' ) , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , RAM_READ_S , BLOCK_RD_S , BLOCK_WR_S , CS_LOW_S , DATA_LOW_S , DATA_HIGH_S )

Records
RegType

Instantiations
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>

The documentation for this design unit was generated from the following file:

Processes

Constants