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AxiLtc2270Deser Entity Reference
Inheritance diagram for AxiLtc2270Deser: Collaboration diagram for AxiLtc2270Deser:Entities | |
| AxiLtc2270Deser.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLtc2270Pkg | Package <AxiLtc2270Pkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| DELAY_INIT_G | Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) ) |
| IODELAY_GROUP_G | string := " AXI_LTC2270_IODELAY_GRP " |
Ports | ||
| clkInP | in | sl |
| clkInN | in | sl |
| clkOutP | out | sl |
| clkOutN | out | sl |
| dataP | in | Slv8Array ( 0 to 1 ) |
| dataN | in | Slv8Array ( 0 to 1 ) |
| orP | in | sl |
| orN | in | sl |
| adcValid | out | slv ( 0 to 1 ) |
| adcData | out | Slv16Array ( 0 to 1 ) |
| dmode | in | slv ( 1 downto 0 ) |
| delayin | in | AxiLtc2270DelayInType |
| delayOut | out | AxiLtc2270DelayOutType |
| axiClk | in | sl |
| axiRst | in | sl |
| adcClk | in | sl |
| refclk200MHz | in | sl |
The documentation for this design unit was generated from the following file:
- devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd
