AxiLtc2270Core Entity Reference

Inheritance diagram for AxiLtc2270Core:

Collaboration diagram for AxiLtc2270Core:

Entities
AxiLtc2270Core.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiLtc2270Pkg	Package <AxiLtc2270Pkg>

Generics
TPD_G	time := 1 ns
DMODE_INIT_G	slv ( 1 downto 0 ) := " 00 "
DELAY_INIT_G	Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
IODELAY_GROUP_G	string := " AXI_LTC2270_IODELAY_GRP "
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32
AXI_CLK_FREQ_G	real := 200 . 0E + 6

Ports
adcIn	in	AxiLtc2270InType
adcOut	out	AxiLtc2270OutType
adcInOut	inout	AxiLtc2270InOutType
adcValid	out	slv ( 0 to 1 )
adcData	out	Slv16Array ( 0 to 1 )
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
axiClk	in	sl
axiRst	in	sl
adcClk	in	sl
refclk200MHz	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd