AxiLiteToDrpIpIntegrator Entity Reference

Inheritance diagram for AxiLiteToDrpIpIntegrator:

Collaboration diagram for AxiLiteToDrpIpIntegrator:

Entities
AxiLiteToDrpIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
EN_ARBITRATION_G	boolean := false
TIMEOUT_G	positive := 4096
ADDR_WIDTH_G	positive range 1 to 32 := 16
DATA_WIDTH_G	positive range 1 to 32 := 16

Ports
axilClk	in	sl
axilRst	in	sl
drpClk	in	sl
drpRst	in	sl
S_AXI_AWADDR	in	slv ( ADDR_WIDTH_G+ 1 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( ADDR_WIDTH_G+ 1 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
drpGnt	in	sl := ' 1 '
drpReq	out	sl
drpRdy	in	sl := ' 0 '
drpEn	out	sl
drpWe	out	sl
drpUsrRst	out	sl
drpAddr	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
drpDi	out	slv ( DATA_WIDTH_G- 1 downto 0 )
drpDo	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

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The documentation for this design unit was generated from the following file:

• axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd