AxiLiteSrpV0.rtl Architecture Reference

Architecture >> AxiLiteSrpV0::rtl

Processes
comb	( axilRst , r , rxFifoAxisMaster , sAxilReadMaster , sAxilWriteMaster , txFifoAxisSlave )
seq	( axilClk )
comb	( axilRst , r , rxFifoAxisMaster , sAxilReadMaster , sAxilWriteMaster , txFifoAxisSlave )
seq	( axilClk )

Constants
INTERNAL_AXIS_CFG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_COMP_C )
TIMEOUT_COUNT_C	integer := 156250000
REG_INIT_C	RegType := ( state = > WAIT_AXIL_REQ_S , txnCount = > ( others = > ' 0 ' ) , timeoutCount = > ( others = > ' 0 ' ) , sAxilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , sAxilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , txFifoAxisMaster = > AXI_STREAM_MASTER_INIT_C , rxFifoAxisSlave = > AXI_STREAM_SLAVE_INIT_C )

Types
StateType	( WAIT_AXIL_REQ_S , WAIT_AXIS_RESP_S , BLEED_S )

Signals
rxFifoAxisMaster	AxiStreamMasterType
rxFifoAxisSlave	AxiStreamSlaveType
txFifoAxisMaster	AxiStreamMasterType
txFifoAxisSlave	AxiStreamSlaveType
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
txaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
rxaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
txaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
rxaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiLiteSrpV0.vhd
• protocols/srp/rtl/AxiLiteSrpV0.vhd