AxiLiteSlave.rtl Architecture Reference

Architecture >> AxiLiteSlave::rtl

Processes
comb	( ack , axilReadMaster , axilRst , axilWriteMaster , r )
seq	( axilClk , axilRst )
comb	( ack , axilReadMaster , axilRst , axilWriteMaster , r )
seq	( axilClk , axilRst )

Constants
REG_INIT_C	RegType := ( toggle = > ' 0 ' , req = > AXI_LITE_REQ_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteSlave.vhd
• build/SRC_VHDL/surf/AxiLiteSlave.vhd