AxiLiteSaciMasterTb.sim Architecture Reference

Architecture >> AxiLiteSaciMasterTb::sim

Processes
ackproc
AXIL
ackproc
AXIL

Constants
TPD_G	time := 1 ns
AXIL_CLK_PERIOD_G	real := 8 . 0E - 9
AXIL_TIMEOUT_G	real := 1 . 0E - 3
SACI_CLK_PERIOD_G	real := 1 . 0E - 6
SACI_CLK_FREERUN_G	boolean := false
SACI_NUM_CHIPS_G	positive range 1 to 4 := 4
SACI_RSP_BUSSED_G	boolean := false

Signals
saciClk	sl
saciCmd	sl
saciSelL	slv ( SACI_NUM_CHIPS_G- 1 downto 0 )
saciRsp	slv ( ite ( SACI_RSP_BUSSED_G , 0 , SACI_NUM_CHIPS_G- 1 ) downto 0 ) := ( others = > ' 0 ' )
axilClk	sl
axilRst	sl
axilRstL	sl
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType
rstLoopL	slv ( SACI_NUM_CHIPS_G- 1 downto 0 )
exec	slv ( SACI_NUM_CHIPS_G- 1 downto 0 )
ack	slv ( SACI_NUM_CHIPS_G- 1 downto 0 ) := ( others = > ' 0 ' )
readL	slv ( SACI_NUM_CHIPS_G- 1 downto 0 )
cmd	slv7Array ( SACI_NUM_CHIPS_G- 1 downto 0 )
addr	slv12Array ( SACI_NUM_CHIPS_G- 1 downto 0 )
wrData	slv32Array ( SACI_NUM_CHIPS_G- 1 downto 0 )
rdData	slv32Array ( SACI_NUM_CHIPS_G- 1 downto 0 )

Instantiations
u_axilitesacimaster2	AxiLiteSaciMaster <Entity AxiLiteSaciMaster>
u_sacislave2_1	sacislave2
u_dualportram_1	DualPortRam <Entity DualPortRam>
u_clkrst_1	ClkRst <Entity ClkRst>
u_axilitesacimaster2	AxiLiteSaciMaster <Entity AxiLiteSaciMaster>
u_sacislave2_1	sacislave2
u_dualportram_1	DualPortRam <Entity DualPortRam>
u_clkrst_1	ClkRst <Entity ClkRst>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiLiteSaciMasterTb.vhd
• protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd