AxiLiteRingBufferIpIntegrator Entity Reference

Inheritance diagram for AxiLiteRingBufferIpIntegrator:

Collaboration diagram for AxiLiteRingBufferIpIntegrator:

Entities
AxiLiteRingBufferIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
EXT_CTRL_ONLY_G	boolean := false
REG_EN_G	boolean := true
DATA_WIDTH_G	positive range 1 to 32 := 32
RAM_ADDR_WIDTH_G	positive range 1 to 19 := 4

Ports
dataClk	in	sl
dataRst	in	sl
dataValid	in	sl
dataValue	in	slv ( DATA_WIDTH_G- 1 downto 0 )
bufferEnable	in	sl
bufferClear	in	sl
axilClk	in	sl
axilRst	in	sl
S_AXI_AWADDR	in	slv ( RAM_ADDR_WIDTH_G+ 2 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( RAM_ADDR_WIDTH_G+ 2 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd