AxiLitePMbusMaster Entity Reference

Inheritance diagram for AxiLitePMbusMaster:

Collaboration diagram for AxiLitePMbusMaster:

Entities
AxiLitePMbusMaster.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
I2cPkg	Package <I2cPkg>
vcomponents

Generics
TPD_G	time := 1 ns
I2C_ADDR_G	slv ( 6 downto 0 ) := " 1010000 "
I2C_SCL_FREQ_G	real := 100 . 0E + 3
I2C_MIN_PULSE_G	real := 100 . 0E - 9
AXI_CLK_FREQ_G	real := 156 . 25E + 6

Ports
scl	inout	sl
sda	inout	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axilClk	in	sl
axilRst	in	sl

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The documentation for this design unit was generated from the following file:

• protocols/pmbus/rtl/AxiLitePMbusMaster.vhd