AxiLiteMasterProxy.mapping Architecture Reference

Architecture >> AxiLiteMasterProxy::mapping

Processes
comb	( ack , axiRst , r , sAxiReadMaster , sAxiWriteMaster )
seq	( axiClk , axiRst )
comb	( ack , axiRst , r , sAxiReadMaster , sAxiWriteMaster )
seq	( axiClk , axiRst )

Constants
REG_INIT_C	RegType := ( sAxiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , sAxiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , req = > AXI_LITE_REQ_INIT_C , state = > READY_S , rnw = > ' 0 ' , done = > ' 1 ' , resp = > " 00 " , addr = > ( others = > ' 0 ' ) , data = > ( others = > ' 0 ' ) )

Types
StateType	( READY_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
ack	AxiLiteAckType

Records
RegType

Instantiations
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteMasterProxy.vhd
• build/SRC_VHDL/surf/AxiLiteMasterProxy.vhd